In general, computer systems employ a central processor unit (CPU), a memory (or memories) and a variety of peripherals sometimes referred to as input-output (I/O) devices. Further, in general, these computer members are connected together by a sophisticated main bus device. When a CPU wants to interrogate a peripheral, a set of address signals is sent down the sophisticated bus to all of the peripherals and the particular peripheral which responds to the address signals quite often sets a latch device or a flag device. Thereafter, a strobe signal, or a read signal, or write signal is transmitted and the selected peripheral in response transmits its message to the CPU or alternatively accepts a message from the CPU.
A major problem in the foregoing arrangement is that the physical distance from the CPU to the peripherals, as measured along the bus, is considerable in terms of transmission time. In other words, it takes a finite amount of time for a signal to travel from the CPU to the furthermost connected peripheral. Even though the selected peripheral may be relatively close to the CPU, the system must wait (before any further action is taken) as though the transmitted signal is being sent to the furthermost peripheral. In addition, the main bus lines provide capacitance to the system and the system must wait until the transmitted signals "settle down".
In reviewing the problem, we recognized that the largest percentage of the signals transmitted were from the CPU to the memory and vice versa. We further recognized that if we located the memory close to the CPU and had the frequently transmitted messages operate at a fast time between the CPU and the memory we would improve the overall speed operation of the system. In addition we determined that the memory could operate with a larger address configuration than the peripherals without expensive alterations to the memory. Accordingly we conceived a new approach to handling of the data transmissions. Our new concept enables the new computer system to determine that the address being transmitted is intended for the memory and, if so, the protocol is changed and the signal speed increased but all of the data flow remains over the main bus so that the protocol and speed of transmission is not changed for the peripherals.